As the integration level of semiconductor memory devices, such as DRAM devices, increases, each cell generally is reduced in size. To provide for such reduction in cell size, various techniques have been used to increase cell capacitance by increasing the effective area of a cell capacitor. To increase the capacitor's effective area, stacked-capacitor and trench-capacitor structures, as well as combinations thereof, have been developed.
However, for these structures to be viable, a field effect transistor, a device isolation region, a bit line contact and a storage node contact must all be formed in a DRAM unit cell. Thus, design rules for minimizing area and ensuring adequate process margin are required. These structures may be very difficult to realize when cell area is very small, for example, 0.5 .mu.m.sup.2 or below. In a conventional DRAM structure, the bit line is formed on the surface of a substrate, resulting in lower photolithography process margin.
In an effort to circumvent these technological problems, a buried bit line (BBL) cell in which a bit line is buried in the isolation region of a stacked cell, has been suggested. See the publication "Buried Bit-Line Cell for 64Mb DRAMs" by Y. Kohyama et al., '91 Symposium on VLSI Technology, pp. 17-18. This structure includes a bit line which is buried in the device isolation region, and a lateral bit line contact which is formed to achieve maximum area efficiency within a small area.
The above BBL cell will be described by referring to the attached drawings FIGS. 1, 2 and 3A-3E. FIG. 1 is a plan view of mask patterns for fabricating a conventional BBL cell. Here, respective mask patterns are shown for defining a first field oxide film denoted by reference numeral 2, a bit line denoted by reference numeral 3, a bit line contact denoted by reference numeral 4, a gate electrode denoted by reference numeral 5, and a storage electrode denoted by reference numeral 6.
FIG. 2 is a vertical section view of FIG. 1 in the X-axis direction. Here, a first field oxide film 2 is formed to define a device isolation region on a semiconductor substrate, and the bit line 3 is buried under the surface of the substrate. The bit line contact 4 for making contact with the drain protrudes laterally from the bit line 3.
FIGS. 3A-3E are vertical section views of FIG. 1 in the Y-axis direction, showing the steps of fabricating the BBL cell structure of FIGS. 1 and 2.
Referring to FIG. 3A, the first field oxide film 2 (FIG. 2) is formed by a general device isolation method, such as a LOCOS method. Then, using a silicon nitride pattern 14 as a mask, trenches are formed in the semiconductor substrate 10, and a second field oxide film 12 is formed along the inner walls of the trenches.
Referring to FIG. 3B, a photoresist 16 is coated on the resultant structure including the second field oxide film 12. Thereafter, the photoresist 16 is patterned, thereby defining an area for forming a lateral bit-line contact therein.
Referring to FIG. 3C, the lateral bit-line contact for making contact between the bit line and the substrate is formed by etching the second field oxide film 12, using the photoresist pattern as an etch mask. A thin polysilicon layer 17 is formed by depositing polysilicon on the surface of the resultant structure, including the lateral bit-line contact. Arsenic ions are then implanted into the substrate 10, thereby forming a source/drain 18.
Referring to FIG. 3D, bit lines 20 are formed by depositing a bit line material such as polysilicon or a refractory metal silicide on the surface of the resultant structure and etching back the resultant structure. The polysilicon layer 17 (see FIG. 3) formed on the silicon nitride pattern 14 is removed.
Referring to FIG. 3E, a third field oxide film 22 is formed on the substrate 10 having the bit lines 20 formed therein, and the silicon nitride pattern 14 (see FIG. 3D) is removed. Thereafter, the gate electrode of the field effect transistor and a capacitor are formed by conventional methods.
According to the above BBL cell structure, step coverage is improved by burying the bit line in the device isolation region of the cell, thereby facilitating the formation of fine patterns. Consequently, the DRAM cell area can be reduced.
In the above-described conventional BBL cell structure, however, it may be necessary to perform a device isolation process twice: once for forming a trench device isolation region having a buried bit line, and once for forming a device isolation region through which the gate runs. Also, photolithography may need to be performed twice for forming the bit line and the bit-line contact, respectively. Accordingly, the manufacturing process may become complex.